Exemplary embodiments of the present invention relate to a method for fabricating a latency control circuit, and more particularly, to a latency control circuit efficiently performing a latency control operation.
When operations are performed between plural semiconductor devices, a predetermined latency occurs from receiving an operational request signal to starting an operation corresponding to the operational request signal. For example, a memory controller outputs a termination command signal and a memory device starts terminating a data pad after a column address strobe (CAS) latency from an input timing of the termination command signal. In order to ensure the reliable processing of the operations between the semiconductor devices, it is important to properly control the latency. A latency control circuit is used for controlling the latency.
A conventional method for controlling a latency of a termination command signal is disclosed in Korean Patent Application No. 10-2006-0049027, herein incorporated by reference. The conventional method uses two clocks, i.e., an internal clock and an external clock having different domains from each other, and two counters respectively allocated to the clocks. For performing reliable operations, the conventional method should continuously provide the clocks even for an asynchronous mode and, therefore, the power consumption increases.